Research on the security and efficiency of the hot

2022-10-22
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Research on the security and efficiency of arm interrupt processing

Abstract This paper focuses on the analysis of a variety of interrupt processing of ARM processor, including common interrupt processing, task switching interrupt processing, reentrant interrupt processing and context saving technology of reentrant interrupt processing based on priority, and gives the program to implement it. It has practical value for ordinary front and rear systems and embedded systems with OS

keyword arm interrupt efficient security context saving

introduction

the RISC processor commonly used in embedded systems is the arm core, which has the characteristics of small size, low power consumption, low cost and high cost performance ratio. However, no matter what type of ARM processor it is or whether there is an operating system in the embedded system, interrupt processing, especially IRQ interrupt, is always necessary, and the core problem of interrupt processing is the preservation of context. Whether the context can be saved safely and efficiently will affect the performance and stability of an embedded system. The author analyzes and summarizes the context saving technology of common interrupt processing, task switching interrupt processing, reusable interrupt processing and reusable interrupt processing based on priority of ARM processor. In order to ensure the correctness of the theory, the core program code has been tested by experiments

1 introduction to system interrupt processing

arm processor interrupts mainly include two types: IRQ common interrupt and FIQ fast interrupt. Fast interrupts are essentially not much different from ordinary interrupts. They have many similarities in processing mechanism. IRQ interrupts are the most frequent and affect the system performance most, so its research and processing is also the most valuable

the working process of ARM processor when IRQ exception occurs is briefly introduced below. When IRQ interrupt occurs, the hardware of ARM processor will automatically perform the following work:

① save the CPSR value of the interrupted task mode to the SPSR register in IRQ mode

② save the PC value of the interrupted task mode to the LR register in the IRQ mode

③ automatically switch the mode to IRQ mode, and disable the occurrence of subsequent IRQ interrupt at bit7 position 1 in CPSR

④ the PC is given an address value of 0xl8, and the program will be executed from 0xl8. Combined with figure 1, we can better understand the working process of arm interrupt processing mechanism

2 ordinary interrupt processing

some ARM embedded systems may have low requirements for interrupts, that is, after an interrupt occurs, first query the corresponding interrupt source, then interrupt the service, and finally return from the interrupt service program to the interrupted place to continue running the program. How to handle interrupts safely and efficiently in this simple application? Security means that the context is well preserved and not destroyed when an interrupt occurs. Efficiency means that as few registers as possible are saved (of course, it is based on Security). It can be seen from Figure 1 that in normal interrupt processing, interrupt service can run in IRQ mode. According to the call rules of atpcs, the ARM compiler saves the R4 ~ R11 registers in the subroutine call, so it is not necessary to save them again. Then the remaining registers must be saved to prevent them from being destroyed after returning from the interrupt service program. Processing code can be written in assembly language and C language. First, assume that the IRQ stack has been correctly established in the initialization code

all enabled queries and services

; Interrupt all services at the same time to improve efficiency

ldmfd SP!, {R0-R3,R12,R14} ; Recovery context

it is not necessary to save SPSR in the above save context. Because in the non nested interrupt handler, it will not be destroyed by any sequence of interrupts

if the processing program is written in C language, the keyword IRQ can be used to explain it, so as to tell the compiler to realize the following operations:

① save the damaged register specified by.Atpcs

② save registers used in other interrupt handlers

the international influence of the plastic extruder industry continues to rise ③ at the same time (LR Bayer has invested about US $120million in the process and environmental protection improvement of the plant 4) is given to the program counter PC to realize the return of interrupt programs and restore the contents of CPSR registers

the C language program of ordinary interrupt processing can be written in the following format:

it can be seen that whether they are written in C language or assembly language, their working principles are the same. Figure 2 shows the saving diagram of arm register in the process of ordinary interrupt processing (dotted line refers to stack saving, solid line refers to stack recovery). The figure corresponds to the steps of program processing, which can help understand the saving process of processor context

3 task switching

in embedded systems with operating systems, the occurrence of interrupts requires that the contents of all registers be saved to the task stack. It is not based on security considerations because interrupts may lead to task switching. When task switching occurs, the register values of all tasks should be saved to the stack of the task. The context of the next task will be restored from the task stack to the processor register. The following analyzes this problem and gives the program code. From the storage of interrupt processing registers in Figure 1, it can be seen that the values of CPSR and PC registers of the task after the interrupt occur are in SPSR and LR of IRQ mode, so it is impossible to simply switch to the mode of task operation. The range of a single set of devices reaches 10000 tons/year, otherwise the CPSR and PC when the interrupted task returns will not be visible (because they are stored in the special registers of IRQ mode and cannot be operated in other modes). At this time, you can consider setting some variable areas as a medium to transfer them to the stack of task operation mode

let's assume that task switching is running in SVC mode. Combined with the above analysis, you can have the schematic diagram of saving task switching shown in Figure 3 (the dotted line is stack pressing saving, the solid line is stack popping recovery; lr_frame and spsr_frame are variable areas)

combined with the steps in the task switching interrupt processing in Figure 3, the corresponding interrupt processing program can be written in assembly language:

4 reentrant interrupt

if you want to respond to other interrupt requests while processing interrupts to shorten the interrupt delay, you must design a reentrant interrupt. Reentrant interrupt is a method to deal with multiple interrupts, but it also brings new problems. In IRQ interrupt mode, if IRQ interrupt is directly re allowed, the address returned by the subroutine is saved in LR because a bl instruction is executed_ IRQ, and here the interrupt occurs. The new interrupt will load its return address into LR_ In IRQ, the return address of the old interrupt subroutine will be overwritten at this time, resulting in system disorder. In this case, LR_ IRQ stack pressing, such as program statements:

but the possibility of interruption before saving LR cannot be ruled out. To solve the above LR_ If IRQ is damaged, the processor mode must be switched. It is common to switch to SVC processing mode. In SVC mode, when calling subroutines through BL, the return address will be saved in LR_ SVC. At this time, the new interrupt occurs (because it will save the return address to lr_irq instead of lr_svc), and the return address of the subroutine in the old interrupt will not be destroyed. It is clear to write reentrant interrupt code based on the above principle analysis. However, in order to ensure the efficiency of processing, interrupt should be allowed as early as possible to shorten the delay. After saving LR_ IRQ and SPSR_ After IRQ, switch to SVC mode immediately and allow interruption again, as shown in Figure 4 (dotted line refers to stack pressing and saving, and solid line refers to stack snapping and recovery)

combined with the processing steps in Figure 4, you can clearly write the assembly language program for reentrant interrupt processing:

5 priority based reentrant interrupt

this situation may occur in the above heavy human interrupt. A high priority interrupt is interrupted by another low priority interrupt because the interrupt request is re allowed in the interrupt service program, Therefore, high priority interrupts have to wait until the completion of low priority interrupts before continuing to operate. In this way, the delay of high priority interrupt service will increase even more. In order to reduce the delay of the above high priority interrupts, priority based reusable interrupts are especially introduced. Its principle is: in the interrupt service program, only other interrupt sources higher than this interrupt are allowed to request interrupts, so a high priority interrupt will be serviced first than a low priority interrupt, which is necessary in most embedded systems. The method adopted is that when an interrupt of a certain priority occurs, the interrupt lower than or equal to the priority can be masked by using the mask bit in its interrupt handler. It should be noted that the value of the original interrupt register should be restored when exiting this interrupt. Assume here that there are several interrupt registers (in fact, many processors of arm have such interrupt control registers): irqmask, interrupt source mask register; Irqstatus, interrupt flag register; Irqclear, clear the interrupt flag register. At the same time, assuming that the priority of interrupts decreases from high (bit31) to low (bito), the following mask variable values can be predefined first:

the context saving of this program is basically the same as that of reusable interrupt processing. For the added part, for example, the coaxiality between the cylinder sleeve and the 10 head slide cannot reach the specified required value, and the different axes of the piston rod and the cylinder sleeve are equal to the query and setting of the interrupt shielding code, the corresponding processing steps can be referred to figure 4

conclusion

this paper focuses on the security and efficiency of context preservation of ARM processor in various interrupt processing, and analyzes various interrupt processing schemes combined with processor structure diagram and program code. It has universal value for ARM processors and is not limited by hardware from different manufacturers

the program source code involved in this paper has been tested on adsl.2 development environment and SEP4020 development evaluation board. Experiments show that this interrupt processing technology is safe and efficient

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